The present application relates to electronic devices, and more specifically to electrostatic discharge (ESD) protection devices for protecting integrated circuits from ESD damage.
Grounded base N-type metal-oxide-silicon (NMOS) devices have been used for (ESD) protection in integrated circuits. FIG. 1 illustrates a conventional grounded substrate NMOS ESD protection device 100. As shown in FIG. 1, NMOS device 100 includes a polysilicon gate 110 over a P-type substrate or a P-well 120 formed in a semiconductor substrate. NMOS device 100 further includes a N+ source 130 and a N+ drain 140 formed in the P-type substrate or P-well 120. The gate 110 and the source 130 are tied to the ground, and so is the P-type substrate or P-well 120, while the drain 140 is connected to a drain node 141. A parasitic NPN bipolar transistor formed by the N+ drain 140 (as the collector), the P-type substrate or P-well 120 (as the base), and the N+ source 130 (as the emitter) is associated with the NMOS device 100. Thus, NMOS device 100 uses the grounded substrate 120 to cause a break down of the drain to substrate junction 125 in response to an ESD pulse on the drain node 141. The breakdown in turn causes the parasitic bipolar transistor to turn on to discharge the ESD pulse.
The above ESD protection scheme suffers from several disadvantages. First, using the drain to substrate breakdown to turn on the parasitic bipolar transistor results in localized current discharge and non-uniform ESD protection. It also requires a large size for the NMOS device 100 in order to dissipate the heat generated by the localized ESD current. A larger NMOS device contributes larger capacitance and is thus not suitable for high speed protection.
In addition, the junction breakdown voltage of the NMOS device 100 is very close to the oxide breakdown voltages of core transistors in the integrated circuits and is thus not suitable for gate oxide protection. Therefore, there is a need for a more advanced ESD protection device than conventional grounded substrate NMOS devices.